idw - Informationsdienst
Wissenschaft
06/30/2004 - 06/30/2004 | Ulm
The 3D-SoftChip is a combination of state-of-the-art processing and interconnection technology. It comprises the vertical integration of two chips (a Configurable Array Processor and an Intelligent Configurable Switch) through indium bump 3D interconnections. The Configurable Array Processor (CAP) is an array of heterogeneous processing elements (PEs) while the Intelligent Configurable Switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer along with a Direct Memory Access (DMA) controller. This seminar discusses the 3D-SoftChip architecture for real-time communication and multimedia signal processing and describes the HW/SW co-design and verification methodology.
Information on participating / attending:
Date:
06/30/2004 17:00 - 06/30/2004 19:00
Event venue:
Oberer Eselsberg, Universität West, Hörsaal 45.2
89081 Ulm
Baden-Württemberg
Germany
Target group:
Scientists and scholars, Students
Email address:
Relevance:
local
Subject areas:
Electrical engineering, Energy
Types of events:
Entry:
06/02/2004
Sender/author:
Peter Pietschmann
Department:
Presse- und Öffentlichkeitsarbeit
Event is free:
unknown
Language of the text:
German
URL of this event: http://idw-online.de/en/event11418
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