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Artificial intelligence works fast, but its energy consumption is growing rapidly. A German-Taiwanese research team is now developing a solution: new memory for leading chip technologies smaller than 3nm. These innovative nanosheet devices enable computing operations directly in memory, thereby drastically reducing energy consumption. They are based on ferroelectric field-effect transistors (FeMFETs) made from hafnium oxide, which are particularly efficient. With a joint research program, Fraunhofer IPMS, Fraunhofer IMWS and the Taiwanese research institute TSRI are laying the foundation for the next generation of energy-efficient AI chips–from smartphones and automobiles to medical devices.
Given the rapidly growing demand for artificial intelligence (AI) and neuromorphic computing, the energy consumption of data centers and edge systems is increasing dramatically. A key bottleneck is the transfer of data between main memory and the computing unit. A joint German-Taiwanese project aims to address precisely this issue: innovative memory technology will enable computing “directly in memory”, with significantly lower latency and energy consumption.
“We are designing a platform that more closely links the memory technology and computing power of state-of-the-art chips. This opens new possibilities for AI systems while reducing energy consumption,” says Dr. Maximilian Lederer, project manager at Fraunhofer IPMS.
Hafnium oxide-based ferroelectric FETs (FeFETs) are considered particularly suitable for this purpose: thanks to thin hafnium oxide layers, the technology can be integrated into modern semiconductor processes. In addition, these components operate capacitively (rather than resistively) and thus consume up to about 100 times less energy in embedded systems than comparable non-volatile memory solutions.
The goal of the collaboration is to establish a 300 mm research line that develops memory not only for consumer applications, but also for automotive, industrial, and medical technology.
“The German-Taiwanese cooperation combines key competencies – from material development and high-resolution material characterization to state-of-the-art device architectures. Together, we are creating a platform for the next generation of energy-saving memory technologies,” adds Dr. Chien-Nan Liu, Director General of the Taiwan Semiconductor Research Institute, National Institutes of Applied Research (TSRI, NIAR).
Close-up (Dieshot) of ferroelectric memory chips on a 300 mm wafer from Fraunhofer IPMS
Copyright: Fraunhofer IPMS
Kick-off of project NVM Advanced.
Copyright: Fraunhofer IPMS
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Close-up (Dieshot) of ferroelectric memory chips on a 300 mm wafer from Fraunhofer IPMS
Copyright: Fraunhofer IPMS
Kick-off of project NVM Advanced.
Copyright: Fraunhofer IPMS
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